ITK Registration Optimization

From NAMIC Wiki
Revision as of 13:14, 30 March 2007 by Aylward (talk | contribs)
Jump to: navigation, search
Home < ITK Registration Optimization

Goals

There are two components to this research

  1. Identify registration algorithms that are suitable for non-rigid registration problems that are indemic to NA-MIC
  2. Develop implementations of those algorithms that take advantage of multi-core and multi-processor hardware.

Algorithmic Requirements and Use Cases

  • Requirements
    1. relatively robust, with few parameters to tweak
    2. runs on grey scale images
    3. has already been published
    4. relatively fast (ideally speaking a few minutes for volume to volume).
    5. not patented
    6. can be implemented in ITK and parallelized.

Performance Requirements and Use Cases

  • Requirements
    1. Single and multi-core machines
    2. Single and multi-processor machines
    3. AMD and Intel - Windows, Linux, and SunOS
  • Use-cases
    1. Intel quad-core Xeon processors (?)
    2. 6 CPU Sun, Solaris 8 (SPL: vision)
    3. 12 CPU Sun, Solaris 8 (SPL: forest and ocean)
    4. 16 core Opteron (SPL: john, ringo, paul, george)
    5. 16 core, Sun Fire, AMDOpteron (UNC: Styner)

Data

Workplan

  1. Quantify current performance and bottlenecks
    1. Identify timing tools (cross platform, multi-threaded)
    2. For each use-case
      1. Centralized data and provide easy access
      2. Identify relevant registration algorithm(s)
      3. Develop traditional ITK-style implementations
      4. Develop timing tests using implementations and data
    3. Across use-cases
      1. Identify ITK classes/functions common to implementations (e.g., interpolation/resampling)
      2. Develop timing tests specific to these common sub-classes
    4. Compute performance on multiple platforms

Progress Highlights

  1. Quantify current performance and bottlenecks

Related Pages

Performance Measurement